1. Field of the Invention
The present invention relates generally to dual damascene methods for forming patterned conductor layers within microelectronic fabrications. More particularly, the present invention relates to dual damascene methods for forming, with enhanced dimensional control, patterned conductor layers within microelectronic fabrications.
2. Description of the Related Art
Common in the art of microelectronic fabrication when forming patterned conductor layers within microelectronic fabrications is the use of damascene methods.
Damascene methods are inlaid methods, where patterned conductor layers are formed within trenches and vias while employing planarizing methods, such that the patterned conductor layers need not be etched from corresponding blanket conductor layers. Of particular significance within the context of damascene methods are dual damascene methods wherein there is simultaneously formed within a via and an overlapping trench a contiguous patterned conductor stud and conductor interconnect layer while employing a planarizing method.
While dual damascene methods are thus clearly desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, dual damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is often difficult in the art of microelectronic fabrication to form while employing dual damascene methods dual damascene apertures (i.e., vias with trenches overlapping thereover) with enhanced dimensional control.
It is thus desirable in the art of microelectronic fabrication to provide dual damascene methods for forming dual damascene apertures with enhanced dimensional control.
It is towards the foregoing object that the present invention is directed.
Various dual damascene methods having desirable properties have been disclosed in the art of microelectronic fabrication.
Included among the dual damascene methods, but not limiting among the dual damascene methods, are dual damascene methods disclosed within: (1) Avanzino et al., in U.S. Pat. No. 5,705,430 (a dual damascene method employing a sacrificial via fill layer); (2) Chan et al., in U.S. Pat. No. 6,312,874 (a dual damascene method employing dielectric layers formed of low dielectric constant dielectric materials); and (3) Huang et al., in U.S. Pat. No. 6,337,269 (a dual damascene method employing three dielectric layers and three etch stop layers).
Desirable in the art of microelectronic fabrication are additional dual damascene methods which provide dual damascene apertures with enhanced dimensional control.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a dual damascene method for forming a patterned conductor layer within a dual damascene aperture within a microelectronic fabrication.
A second object of the present invention is to provide a dual damascene method in accord with the first object of the present invention, wherein the dual damascene aperture is formed with enhanced dimensional control.
In accord with the objects of the present invention, there is provided a method for forming a dual damascene aperture within a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a patterned first dielectric layer which defines at least part of a via. There is then formed over the patterned first dielectric layer a blanket second dielectric layer deposited such as to incompletely fill the via and form a void within an incompletely filled via. There is then formed over the blanket second dielectric layer an etch mask layer which defines the location of a trench to be formed through the blanket second dielectric layer and overlapping the via. There is then etched the blanket second dielectric layer, while employing the etch mask layer, to form the trench overlapping a re-opened via formed from the incompletely filled via.
The present invention provides a dual damascene method for forming a patterned conductor layer within a dual damascene aperture within a microelectronic fabrication, wherein the dual damascene aperture is formed with enhanced dimensional control.
The present invention realizes the foregoing object when forming the dual damascene aperture by forming over a patterned first dielectric layer which defines at least part of a via a blanket second dielectric layer deposited such as to incompletely fill the via and form a void within an incompletely filled via. Thus, when etching a trench through the blanket second dielectric layer in a fashion such as to re-open the incompletely filled via and form therefrom a re-opened via, the re-opened via within the dual damascene aperture is formed with enhanced dimensional control since the void provides for more efficient and uniform etching of portions of the blanket second dielectric layer formed within the incompletely filled via when forming the re-opened via therefrom.